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This could be a couple of things.
Have you asserted source_ready?
Have you included a global clock enable, which will also need to be asserted?
What are you using for your input?
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Thanks, I got it done by using a small state machine to control sop and eop, the source_ready is set to '1'. and then WAIT for 2x1024 clock cycles. I didin't wait for such a long time.
But still question, why distance between sop and eop is 1024? what 's different if I use distance between sop and eop other than FFT points?
By the way, I didn't use **** enable. Is that ok?
The use 8 bit input for PRN code. That's wasted!!!! ]
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