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Altera_Forum
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9 years ago

Precise sampling rate and decimation

Hi there, I have spent some time making a MAC based digital 1000 tap filter on a DE1 board. The ADC rate into the filter module is 40khz... However i would like to down sample my data. I am aware of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Thanks rsefton, Ill check it out;)

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you can design "variable rate converter" or call it variable decimator in the FPGA. It is a bit of learning curve. It requires plenty memory for coefficients but only uses few of them at a time.