PLL Reconfiguration read of PLL registers

Hi Shmuel

Thanks for your inquiry. Allow me to understand your issue. May I know which device you are using and if possible, can you attach more details or share the design?

Thanks.

Eng Wei

Dear Eng Wei,

Thanks for getting back to me.

I am using a Cyclone V. I have compiled a design with a PLL that has been set to 25MHz. I have also included a Qsys system where the NIOS has been connected to a Altera PLL Reconfig component. The reconfig_to_pll and reconfig_from_pll signals have both been exported and connected to the external PLL in accordance to AN661. I have also generated a .mif file that will allow me to reconfigure the PLL to 125MHz. We initially wrote firmware that would just go ahead and read the Reconfiguration Registers in order to read the current values that were compiled with the design. Our plan was once we have confirmed this then we were going to re-program the PLL and then re-read the register and check the new values (as well as see the change of the clock frequency via a scope). When we tried this initial read of the reconfiguration Registers we unfortunately we only read zero values. However the clock in fact was measured as 25MHz as expected. We performed a regular NIOS read from the registers based upon the "Table 2: Fractional PLL Dynamic Reconfiguration Registers and Settings" found in the AN661. Is there something we are doing wrong ?

Thanks again for all your help

Bets regards

Shmuel

Hi Shmuel

There is a sample design (with .qar) mentioned in the section "1.4.6. Design Example 5: .mif Streaming Reconfiguration" in the doc https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn1425632318141

You can take the example and cross check with your design implementation.

Thanks.

Eng Wei