Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

PLL IP Core

Hi, I'm interesting to use clock dividing/multiplication. Use the IP MegaWizard ALTPLL. As i have seen in datasheet, before the MegaWizard function will start work, the asynchronous reset (areset ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If You're getting X on the output, maybe signal has no initial value? That could be a bug also. Probably nobody would simulate PLL core to get higher frequency in the simulation.