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FPGA_World's avatar
FPGA_World
Icon for New Contributor rankNew Contributor
5 years ago
Solved

PFL IP core causing Flash access error

I am Interfacing Intel FPGA Cyclone V (5CEBA5F), MAX V CPLD (5M1270Z) with Flash (S29GL01GT) to configure and store data. I am using CPLD and Flash device to configure the FPGA. In CPLD, I have imp...
  • FPGA_World's avatar
    FPGA_World
    5 years ago

    To reach the solution, I tried following solutions

    1) Init_done signal from FPGA is feedback to one of the FPGA's input pin and enable all the FPGA logics AFTER "Init_done" is high.

    2) Reset the Flash device after Init_done is high and before writing data to Flash.

    3) Use "Flash_ready" signal to verify the Flash state after reset.

    I hope this helps.

NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi,


If there is no further information needed, I will proceed to close this case.


Thanks.


Regards,

Aiman


  • FPGA_World's avatar
    FPGA_World
    Icon for New Contributor rankNew Contributor
    5 years ago

    To reach the solution, I tried following solutions

    1) Init_done signal from FPGA is feedback to one of the FPGA's input pin and enable all the FPGA logics AFTER "Init_done" is high.

    2) Reset the Flash device after Init_done is high and before writing data to Flash.

    3) Use "Flash_ready" signal to verify the Flash state after reset.

    I hope this helps.