PFL - Flash queries

Hi,

Please find my response below:

We are not trying to alter the .pof bitstream content. The .pof gets generated automatically by the 'convert programming files' option in Quartus as I stated already in my ticket. Yes, I am aware that we need to make sure that the image size will not override any other image size. The 'convert programming files' tool warns us during the .sof -> .pof conversion. If any such conflict exists it will not generate the .pof and flag it for attention.

We are planning to use our existing I2C slave controller within our Cyclone V FPGA to send the .pof bitstream to the flash (

1) through the PFL? Don't think it's through the PFL. Looks like it will go directly to the flash because our FPGA has direct link to the Flash Address/Data/Control lines. Do you agree here ?

Through PFL if the bitstream is sent from MAX V to FLASH. Through I2C / any interface on your design between FLASH and FPGA if there is any if you are sending the bitstream from FPGA to FLASH.

from an external host via I2C. But need to make sure we can write to the flash in a way that PFL can recognize.

FPGA will be receiving via I2C address/data information from the external host in bytes and I will need to translate it into words format and send this to the flash in a way the PFL can recognize it. Need to know how the PFL data structure is implemented.

2) What I was asking is it all pure data (ie no hidden special headers to worry about?) within the .pof file of the PFL data structure apart from the option bits part? :

BLOCK START ADDRESS END ADDRESS

Page_0 0x00000000 0x0041241B

Page_1 0x00420000 0x0083241B

Page_2 0x00840000 0x00C5241B

OPTION BITS 0x00C54000 0x00C54080

I think you can just directly write the POF into the flash memory. Since you are using PFL for FPGA configuration, the PFL IP needs to read the header from the bitstream. Thus, there is no need to remove the header or whatsoever. Just write the entire POF into the flash will do.

3a) If the OPTION_BITS start address is changed (as the example above), I believe that the PFL IP we generate for just FPGA Configuration (ie not FPGA Programming), the FPGA Configuration parameter “What is the byte address of the option bits, in hex?” before re-generating it has to change from 0x00000000 to 0x00C54000. Is this the case ? Please confirm

Yes, you need to change in the IP as well, then regenerate.

3b) The PFL we generate just for 'Flash Programming' does not specify any option bits parameter to setup like the FPGA Configuration one does. Is this the case? Please confirm

Yes it is correct.

Above example has no conflict of any page addressing involved and complies with the boundary rules.

4a) So from this above info could I assume that eg Page_1 in x16 it will be possible to write 256 words of pure data per Line Buffer to the flash as follows ?

Page_1 : 0x00420000, End address: 0x0083241B -> (4.269083MB of data)

If you are using PFL, the FIFO is limited to the setting you choose.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf (Page 32)

4b) These were reported as byte addresses within the .map file. Our flash data line is 16 bits and from FPGA we with our current system (no remote upgrade image sent to the flash yet) can process data and write it to the flash. So this .pof file byte-to-word addressing before data gets into the flash must be happening here. Is this the case?

Upper address bits (27:16) determine the Sector 66 -> 131 (ie total of 66 sectors)

4.269083MB uses Flash Sectors: 0 -> 65 (i.e a total of 66 Sectors)

-> 256 Line Buffers per sectors 0-64 are used (256 Words per Line Buffer)

-> Last 66th Flash Sector (ie no 65) uses 36 Line Buffers (256 Words per Line Buffer) + 1 Line buffer (27 Words)

Yes.

Thank You.