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JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

PCtoFPGA AVMM DMA data-transfer cann't complete in time randomly using A10 PCIe AVMM IP

hello experts, we are using A10 HIP AVMM IP design as a PCIe device to pug inside X86 XEON SERVER to work with. In Linux driver, we program FPGA AVMM DMA Engine to transfer bulk-data between...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Could you provide the Signal Tap?


Thanks

Best regards,

KhaiY


JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

Hi @KhaiChein_Y_Intel ,

1) Regarding of " Signal Tap " capture, what signal（s） do you request to capture ？

2) Also regarding of " RxErr+ ", " BadTLP+ Timeout+ ", I believe they are located in PCIe Physical Layer & Link Layer , correct ? Since they're not relatedd to PCIE Application Data, does that mean it may be a Hardware related issue ?

Thanks for feedback //