PCIe without Rate match FIFO

Hi,

Does anybody know why a PCIe IP with rate match FIFO turned off gives the following error during compilation. It would seem to me that the IP should produce code that compiles or at least let the user know if they need to do something further like add assignments. it would seem that removing the FIFO impacts the clocking. Has anybody seen this in QII 7.2 and if so what the fix for it.

Thanks in advance!

Error: Input port CORECLK of GXB Receiver channel "metro_logic_top:u_logic_top|pcie_x4_2:u_pci_e|pcie_x4_2_core:wrapper|altpcie_64b_x4_pipen1b:altpcie_64b_x4_pipen1b_inst|altpcie_serdes_2sgx_x4a_10000:alt2gxb.alt2gxb_10000.2sgx_a.altpcie_serdes_2sgx0_x4a|alt2gxb:alt2gxb_component|channel_rec[0].receive" must be fed by output port CORECLKOUT of GXB Receiver channel "metro_logic_top:u_logic_top|pcie_x4_2:u_pci_e|pcie_x4_2_core:wrapper|altpcie_64b_x4_pipen1b:altpcie_64b_x4_pipen1b_inst|altpcie_serdes_2sgx_x4a_10000:alt2gxb.alt2gxb_10000.2sgx_a.altpcie_serdes_2sgx0_x4a|alt2gxb:alt2gxb_component|channel_rec[0].receive" because GXB Receiver channel do not use Rate Match FIFO