Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThank for your help
I have read this user guide, but there is some problems with this design. I have changed chaining_dma design a bit: I have inverted "local_rdata" signal (that is read data of ddr3) and send this signal to pcie, but at the host side there is no change in read data in software. I guess that the software doesn't read and write in DDR3. Is it correct?