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sambkr's avatar
sambkr
Icon for New Contributor rankNew Contributor
3 years ago

PCie SRNS, separate perstn

Dear Support, I plan to use a PCie switch board to connect a x16 pcie lane inside a PC to 4 FPGA (4 lanes pcie) cyclone 10 GX boards. FPGA boards will be endpoints. The Pcie switch board use mini...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Based on my understanding While the PERST# (reset) signal is an integral part of the PCIe specification and is commonly used to reset and initialize PCIe devices, it is not strictly required for all implementations.

There are certain scenarios where a PCIe hard IP can work without the PERST# signal. For example, if the system ensures that the PCIe device is properly initialized through alternative means, such as software or other hardware mechanisms, the PERST# signal may not be necessary.


For information about reset and link training status you may refer to

https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/reset-status-and-link-training-signals-reset.html

I believe the explanation is better there.


Let me know if further clarification is needed.


Regards,

Wincent_Intel