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sambkr's avatar
sambkr
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2 years ago

PCie SRNS, separate perstn

Dear Support, I plan to use a PCie switch board to connect a x16 pcie lane inside a PC to 4 FPGA (4 lanes pcie) cyclone 10 GX boards. FPGA boards will be endpoints. The Pcie switch board use mini...
Pcie
sambkr's avatar
sambkr
Icon for New Contributor rankNew Contributor
2 years ago

Hi Wincent,

let me summarize what I've understood.

It's possible for the Pcie Hard Ip working without shared perstn pin. Working with Cyclone 10 GX with AVMM design.

Perstn pin is used for "hot reset".

I will connect this pin to nconfig of FPGA.

If the PC reset, how can I get the information of "broken link" and how the endpoint will ask for "hot reset" or "warm reset" or any reset to restart LTSSM for new link training.

is this information into pcie data link layer ? TLP ?

Do I have to create custom logic to drive perstn signal ?

BR.