Forum Discussion
sambkr
New Contributor
New ContributorPCie SRNS, separate perstn
Dear Support, I plan to use a PCie switch board to connect a x16 pcie lane inside a PC to 4 FPGA (4 lanes pcie) cyclone 10 GX boards. FPGA boards will be endpoints. The Pcie switch board use mini...
sambkrNew Contributor
New ContributorHi,
I will use AVMM ref design concerning pcie IP.
Configured GEN2 x4 with DMA.
I don't really get my answer reading your post.
The Pcie switch bord into the will use some PLX Switch, switching 1 x16 lanes into 4 (x4) lanes.
I catch you about connecting hard Ip Pcie reset with nconfig signal.
Could you confirm if the PC reboot, the FPGA PCie IP is able to handle In band reset, and able to reset LTSSM for new link training and enumeration ?
For my test I plan to use the cyclone 10 GX devKit (DK-DEV-10CX220-A), with some custom board to convert from SFF-8644 to PCie riser.
Best regards.
