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PPham3's avatar
PPham3
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7 years ago
Solved

PCIe SRIOV Avalon Stream Gen 3 automatically generate locked read request

Hi all, I have a problem with PCIe SRIOV avalon stream. I used SRIOV example design but tried to take the tx stream and rx stream out of the APP function. When I get those signal to signaltap. I not...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    7 years ago

    You need APPS in order to make your design fully function. Without the APPS, the Host should still detect end points, and I don't aware any specify signal need to be connected.

    Regards -SK ​

PPham3's avatar
PPham3
Icon for New Contributor rankNew Contributor
7 years ago

the reason why I do not want to use the APPS is to generate 4 PFs. at this point, the APPS is not supported (maximum 2 PFs for the APPS).

Still many thing to work since when I generate 2 PFs via example design, each PF has 8 VFs. The linux lspci can detect 1 PF and full 8 VFs, still one more PF missing. Is there any special signal that must be connected to make this design work

?

Thanks so much, SK Lim.