Forum Discussion
PPham3
New Contributor
7 years agoPCIe SRIOV Avalon Stream Gen 3 automatically generate locked read request
Hi all, I have a problem with PCIe SRIOV avalon stream. I used SRIOV example design but tried to take the tx stream and rx stream out of the APP function. When I get those signal to signaltap. I not...
- 7 years ago
You need APPS in order to make your design fully function. Without the APPS, the Host should still detect end points, and I don't aware any specify signal need to be connected.
Regards -SK
SengKok_L_Intel
Regular Contributor
7 years agoHi,
The lock request is performed between a Root Port and the Legacy Endpoint. Perhaps, you may provide more information like what device you are using, or what application you are running and observe this behavior. Are there a concern of memory read or write request?