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Altera_Forum's avatar
Altera_Forum
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13 years ago

PCIe simulation error: TxElecIdle not asserted

Hi,

While simulating PCIe IP core using ModelSim with the testbench generated along with the IP core generation, Iam getting the following error message.

ERROR: 57 ns TxElecIdle not asserted while reset asserted, Lane: 0, MAC: RP

In the waveform obtained, it is found that at any time, either of three resets to the PCIe ip core (crst, npor, srst ) is active high, so that the design is not coming out of reset state and hence txelecidle0_ext is always active high and forces transmit output to electrical idle. Though I tried with another device and by changing parameters for PCIe generation, the result was same.

Expecting your valuable suggestions to overcome this error.

Thanks & Regards,

Gibin George

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi Gibin,

    Please try changing simulation parameters of the generated testbench.

    Check if you are using PIPE/serial PHY interface and set parameters accordingly.

    May be this will be helpful.

    regards,

    umesh