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Altera_Forum
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13 years ago

PCIe simulation error: TxElecIdle not asserted

Hi, While simulating PCIe IP core using ModelSim with the testbench generated along with the IP core generation, Iam getting the following error message. ERROR: 57 ns TxElecIdle not...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Gibin,

Please try changing simulation parameters of the generated testbench.

Check if you are using PIPE/serial PHY interface and set parameters accordingly.

May be this will be helpful.

regards,

umesh