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sglow1's avatar
sglow1
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2 years ago

PCIe root port unable to read endpoint RAM

I've got two boards, both using Cyclone IV FPGAs with hard PCIe IP blocks. One board is a PCIe endpoint and is working great. I can use it in a PC and it's been working well for years. The other ...
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sglow1's avatar
sglow1
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2 years ago

OK, I think I've found my problem.

When reading the IP core user's manual I didn't pay enough attention to the qword alignment of data. As a result, when trying to write to a register that was not qword aligned (i.e. address bit 2 was set) I was putting the data in the wrong place in my TLP.

That's why I couldn't write to some configuration registers. It wasn't that they were read only, it's because I was inadvertently always writing zeros to them.

RTFM I guess, and if you're still having problems, read it again!