PCIe Memory Read completion
hello, i wonder about the pcie protocol.
If you request 4096B from memory read, the completion will return 8 of 512B, but according to the avst interface, there is a module that determines whether the completion buffer has received all the completions.
In this module, if the request is not completed because all completions have not come, can CPLD in Rx queue fail to transmit?
(Eight 512B CPLDs must arrive, and only then do they transmit together?) Or are they transmitted one by one after checking only the buffer?
I'm sorry that I can't speak English well.
Thank you for your reply.
Hi
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