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EastGun-A's avatar
EastGun-A
Icon for New Contributor rankNew Contributor
3 years ago
Solved

PCIe Memory Read completion

hello, i wonder about the pcie protocol. If you request 4096B from memory read, the completion will return 8 of 512B, but according to the avst interface, there is a module that determines whether...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi

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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi EastGun,


Please accept my apology for late reply.

In a typical system design, when you request 4096 bytes from memory read, the system may choose to split the request into smaller chunks for efficient processing. In your case, the completion returns 8 chunks of 512 bytes each. The completion buffer is likely used to hold these individual chunks until all of them have arrived.

Regarding the behavior of the CPLD in the Rx (receive) queue, it depends on the system design and the specific implementation. If the system requires all eight 512-byte chunks to be received before transmitting anything, the CPLD may indeed wait until it has received all the completions in the buffer before transmitting them together.


You can enable the RX buffer limit port to control the buffer limit on the CplD packet under page 138

https://www.intel.com/content/www/us/en/docs/programmable/683059/21-1-4-0-0/introduction.html


Let me know if you need any further clarification.


Regards,

Wei Chuan