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samhuel's avatar
samhuel
Icon for New Contributor rankNew Contributor
4 years ago

PCIe LTSSM debug

Hi FPGA designer, I'am currently working on a custom board. I have a c10GX105 connected in PCIe (x1) to a iMX7 SOM. I have some trouble with PCIe connection. I'am stuck in LTSSM state x"0F", s...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Stuck or stable at LTSSM 0xF or L0 state is expected. Which mean the PCIe link is training up to the final state. What is your expectation on LTSSM state?


Regards -SK


  • samhuel's avatar
    samhuel
    Icon for New Contributor rankNew Contributor
    4 years ago
    On the iMX I don’t see something satisfaying using lspci -v command.
    On my design I use 2 Bar and each are connected to onchip memory.
    Lspci just tell there is a bridge connected and nothing more, don’t see the right size of bar (on chip memory). I know imx limitation (32 bits and 128M of memory max).
    BR.