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Sure, Lukas!
I have a Qsys subsystem inside my design which contains the PCIe core. Inside that, the altpcie_cv_hip_avmm_hwtcl submodule has a number of parameters/generics. The parameter CG_ENABLE_ADVANCED_INTERRUPT exists in altpcie_cv_hip_avmm_hwtcl and quartus should automatically set it when you select legacy interrupt but it doesn't. You have to manually add the generic both to the component declaration and the generic mapping at the instantiation, in your Qsys module.
Insert into the component declaration:
CG_ENABLE_ADVANCED_INTERRUPT : integer := 0;
Generic mapping:
CG_ENABLE_ADVANCED_INTERRUPT => 1,
I'm guessing you are using VHDL at the top level of your Qsys design. I think people using Verilog at the top level don't have this problem.
Altera's promised to fix this in a future version of Quartus.
I hope this was the problem in your case too and you can fix it, with the above mod.
Sandor
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Hello Sandor,
thank you very much for your reply (event Altera support redirected me to your post :)). I also have QSYS subsystem in my design with altpcie_cv_hip_avmm_hwtcl submodule. And yes, I'm using VHDL at the top level of my Qsys design. I tried to perform changes you suggested (you were right, those parameters were not set/used in VHDL generated code) but despite that I was not successful. I can not receive legacy nor msi interrupts.
What I find strange when accessing CRA is that even if I write to enable interrupt register
http://www.altera.com/literature/ug/ug_c5_pcie.pdf#page=167 -> eg. 0xFFFFFFFF and then I try to read the value back I read only zeros. It seems to me that I can read only zeros from CRA. Did you have similar experience ? Reading/Writing from other components on the same BAR over PCIe is no problem.
Please let me know if you have idea.
Thank you very much.
Best regards
Lukas
Honored Contributor
