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Altera_Forum
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13 years ago

PCIe IP Compiler addressing

Hi All,

We had several successful designs with PCIe IP Compiler on Cyclone IV GX using SOPC Builder and Qsys. Now we decided to make our own designs with the same core in Verilog.

I am examining the user's manual of this core and have a lot of questions about it. Maybe these are basics but are not clear for me.

I understand the basic core has Avalon ST interface which transfers the PCIe header also. So a stream interface should be built up which decodes it. But it contains several field. Where can I get information about these fields in the system during runtime? The IDs?

How is the addressing done during runtime? Do this interface give physical addresses? How should I know if my internal modules are addressed or not?

The appendix of the manual does not give any information about these questions.

Where are the control registers of this core? In SOPC Builder/Qsys they are available through the CRA port but here how are they mapped?

Are these information included in the manual? I did not find. I do not know where to start and need for help.

Regards,

Istvan

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