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Honored Contributor
Honored ContributorPCIe IP Compiler addressing
Hi All, We had several successful designs with PCIe IP Compiler on Cyclone IV GX using SOPC Builder and Qsys. Now we decided to make our own designs with the same core in Verilog. I am e...
Altera_ForumHonored Contributor
Honored ContributorI suggest reading the PCI and PCIe Specs from the PCI-SIG. Those clearly state what to do in reaction to a received TLP and how to construct transmit TLPs. The Altera PCI Express User Guide just tells you how you interface these TLPs with the Avalon-ST interface.
You might get a first impression looking at this article (http://billauer.co.il/blog/2011/03/pci-express-tlp-pcie-primer-tutorial-guide-1/), continued here (http://billauer.co.il/blog/2011/03/pci-express-tlp-pcie-primer-tutorial-guide-2/). That is a very brief introduction to the topic, alongside with a lot of advertisment for the author’s solution (Xillybus) which I can neither recommend nor discourage to use because I don’t know it. At least it might be hard to make it work on Altera because it seems to be written solely for Xilinx FPGAs. – Matthias
