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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

PCIe hprxm_master doesn't handle unaligned reads correctly

Hello, we have an Arria 10 PCIe design with MM DMA interface, utilizing hprxm_master (bursting BAR2 rxm) for non-DMA access. Platform designer IP does a good job translating between different clock d...
Pcie
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
I could reduce the test setup reproducing the error to a 32-bit Avalon MM Slave (onchip memory) connected to hprxm master. An unaligned 64-bit read crossing the 256 bit address boundary gets wrong data. I put the test into PCIe_fundamental demonstration project for TR10a-HL development kit.
onchip_memory_2_1 is the 32-bit slave, onchip_memory_2_2 a 256-bit slave that doesn't show the error.

Regards
Frank

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Frank,

Thanks for sharing with me your finding.
Do you test it in Arria 10 device as well ?

Regards,
Wincent_Intel