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jpang10's avatar
jpang10
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5 years ago

PCIe hard IP Bringup on Cyclone 10 GX custom board

Hello, We are having trouble bringing up the PCIe Hard IP on our custom board. The hard IP is set up for gen 1 x1. It appears that coreclkout is stuck low and not toggling. Current setup: We ar...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

To identify if there is FPLL dependency, could you please change the Fpll location by using the following setting in the QSF file?


set_location_assignment FPLL_1CT -to inst|xcvr_fpll_a10_0|fpll_inst

or

set_location_assignment FPLL_1DB -to inst|xcvr_fpll_a10_0|fpll_inst


Besides, how many boards that you encounter this problem?


Regards -SK


jpang10's avatar
jpang10
Icon for New Contributor rankNew Contributor
5 years ago

Hi SK,

I've tried all 4 locations (1CT, 1CB, 1DT, and 1DB) of fpll, and verified that they were placed in the specified location using the chip planner after compiling. FPLL still doesn't output in any of the location, while IOPLL does.

I have a total of 3 boards, and have tried on 2 of them, and they behave the same way. IOPLL works, and FPLL doesn't.

I really appreciate all the help so far. Do you have other suggestions of what I can look into?

  • jpang10's avatar
    jpang10
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi SK,

    My FPLL works after I disabled calibration using
    set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1"

    Would there be an issue if calibration is disabled? It appears that calibration was busy, holding my fpll in reset.

    What could be some possible causes that calibration wasn't able to complete?