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MaHa1's avatar
MaHa1
Icon for New Contributor rankNew Contributor
2 years ago

PCIe hard IP and SerDes Transceiver Configuration in Cyclone V GX with 6 transceivers

Dear Intel Community and Intel Employees, I need to place one PCIe Gen1 x1 hard IP block and 4 SerDes Transceiver Channels of an third party IP of an switch into a Cyclone V GX with 6 transceivers (...
Pcie
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
11 months ago

Hi,

These issues could be due to the way you have split up your reconfiguration controller, where the minimum "granularity" is a triplet, or perhaps the channel placement is constrained because you are using CMU PLLs, which can only be placed in CH1 or CH4 of a 6-pack.

I believe that you should check the clock sharing and the data rates that you are targeting within a bank. Please check the PLL sharing guidelines: 1.5. PLL Sharing


Regards