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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
4 years ago

PCIe Gen3 PHY-IP

I use Stratix10, quartus pro 20.3, I want to generate IP PHY of PCIe, NativePHY IP with PCIe PIPE mode only.

I saw at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_...

Table 99. PIPE Gen3 32 bit PCS Clock Rates p.172

that I can choose, gen 1 will work with clock of 62.5MHz , How can I choose this clock rate and use it for pipe clk ?

the default PCS clkout is 125MHz, and I find no mention of changing the frequency of gen1

Thanks,

Moti

4 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    You will not see the 62.5Mhz for selecting the Gen1 capability only. This is because gen1 is not using 32 bits interface. This 62.5Mhz is referring to when you select Gen3 Capability mode, but it down trained to Gen1.


    Regards -SK


    • Moti's avatar
      Moti
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi

      thanks for the response,

      yes, I choose gen3, but the PCS clk is 125MHz . ( as the img I attached )

      In these default values gen1 will work at 62.5MHz ?

      ​​

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Yes, it should work. Users can use the pipe_rate[1:0] signal to change the data rate.


  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

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