Forum Discussion
Occasional ContributorPCIE example issues
Hi Pieter,
And yes, indeed, if you run the software test as in figure 12, then the application accepts traffic loadup to MAX.PAYLOAD. BUT NOT THE TESTBENCH / APPS in simulation!
Yes. As in my previous reply, the testbench provides simple method to do basic testing and this does not cover all the traffic profile stimuli. If user wants to simulate with what is not covered in the testbench, user has to modify the testbench based on their requirements.
So, i think i am on the edge of improving the testbench and APPS to payload = max.payload. My question: if i would share this code with you, would INTEL be willing to compensate me for this effort ? (i think INTEL does not deliver what it says it does as described in the manual)
I apologize for the miscommunication if there is any. The reason I asked if you are willing to share the modification earlier is because there are some hobbyists share information, what they have created or method to solve problems in this public forum. Please do not share if the content is confidential or non-public accessible.
Thanks for your understanding. Do let me know if you have any questions or concerns.
Best regards,
KhaiY
Regular ContributorHi Pieter,
I apologize for the miscommunication if there is any.
As I explained earlier, the IP can accept TLP up to max payload and the testbench provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. Corner cases and certain traffic profile stimuli are not covered. This is stated in the UG https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf (Page 156).
Please do not share any information that is confidential or non-public accessible. Otherwise, you are always welcome to share in this Public forum.
Thanks
Best regards,
KhaiY
- PVanL
Hi KhaiT,
I still feel we somewhere miss what we are saying to each other:
You say: the TLP can handle any traffic size, as long as it less than the max payload (which can be 128, 256, 512, 1048, 2096 Bytes). For special cornercases, please apply commercial verication IP is recommended.
I say: the testbench and APPS can ONLY handle traffic that is LESS or equal to 4 Bytes. Document UG-01145 says: $16, pag 157: "It can only handle received read requests that are less than or equal to the currently set Maximum payload size option specified under PCI Express/PCI Capabilities heading under the Device tab using the parameter editor. Many systems are capable of handling larger read requests that are then returned in multiple completions." THIS IS NOT TRUE!!!!
See figure 10 on page 21, where you clearly see the 4 bytes reported. IT IS NOT POSSIBLE TO MAKE THIS AS BIG AS MAX.PAYLOAD. I would not call anything larger then 4 bytes a corner case.And yes, indeed, if you run the software test as in figure 12, then the application accepts traffic loadup to MAX.PAYLOAD. BUT NOT THE TESTBENCH / APPS in simulation!
So, i think i am on the edge of improving the testbench and APPS to payload = max.payload. My question: if i would share this code with you, would INTEL be willing to compensate me for this effort ? (i think INTEL does not deliver what it says it does as described in the manual)
regards, Pieter
