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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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PCIE example issues

I am using the PCIE Example as described in UG-20234. As i want to connect another application behind the hard-IP EP, i am modifying the testbench and APPS to allow transfers >4 bytes, which is how t...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi Pieter,


    And yes, indeed, if you run the software test as in figure 12, then the application accepts traffic loadup to MAX.PAYLOAD. BUT NOT THE TESTBENCH / APPS in simulation!


    Yes. As in my previous reply, the testbench provides simple method to do basic testing and this does not cover all the traffic profile stimuli. If user wants to simulate with what is not covered in the testbench, user has to modify the testbench based on their requirements.


    So, i think i am on the edge of improving the testbench and APPS to payload = max.payload. My question: if i would share this code with you, would INTEL be willing to compensate me for this effort ? (i think INTEL does not deliver what it says it does as described in the manual)


    I apologize for the miscommunication if there is any. The reason I asked if you are willing to share the modification earlier is because there are some hobbyists share information, what they have created or method to solve problems in this public forum. Please do not share if the content is confidential or non-public accessible.


    Thanks for your understanding. Do let me know if you have any questions or concerns.


    Best regards,

    KhaiY




KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Pieter,


I plan to generate an example design using the same PCIe settings as pcie_ed.qsys that you have provided but I see warning messages below when I open the pcie_ed.qsys file.


Component Instantiation Warning: pcie_ed.APPS: File not found: ip/pcie_ed/pcie_ed_APPS.ip

Component Instantiation Warning: pcie_ed.DK: File not found: ip/pcie_ed/pcie_ed_DK.ip

Component Instantiation Warning: pcie_ed.DUT: File not found: ip/pcie_ed/pcie_ed_DUT.ip

Component Instantiation Warning: pcie_ed.MEM: File not found: ip/pcie_ed/pcie_ed_MEM.ip

MWr:

DW0 60000002: length = 2, Fmt = 2’b11”, Type = 5’b00000 => strange: Fmt should be 2’b10 for MWr!!!??? (this is made by INTEL IP)

>> Both 2'b010 and 2'b011 are valid for MWr. 2'b010 is for 3DW with data and 2'b011 is for 4DW with data. You are using 4DW so 2'b011 is correct.


DW3 00010000 = ???? (should be data???!!!). But the data arrives correctly in the memory (Made by Intel IP) In reality it is data[31:0]

>> TLP header DW3 and DW4 are for address but not data.


MRd

DW0 20000002: Length = 2, Type = 5’b0000, Fmt = 2’b01 => strange: Fmt should be 2’b00 for Mrd (Made by Intel IP)

>>Both 2'b000 and 2'b001 are valid for MRd. 2'b000 is for 3DW with no data and 2'b001 is for 4DW with no data.


Have you tried using the example design without modification? Do you see any unexpected behavior in the example design without modification?


Thanks

Best regards,

KhaiY


PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Dear KhaiY. Yes, of course i tried without modification It runs fine. Take care: i modified the data being sent, and being send back, by 1/ making them different per loop, and 2/ adding 1 to each byte. Of course the comparator does not like that, so i changed it that it reports a difference, but does not stop as a result of that (other than the design example, where it would stop).

For more input/comments, check the attached word file, and check the transcript line 3640 -- end for the output of the comparator when Byte = 4.
I also attached a transscript_08.txt to show for Bytes = 8

regards, Pieter