Forum Discussion
Occasional ContributorPCIE example issues
Hi Pieter,
And yes, indeed, if you run the software test as in figure 12, then the application accepts traffic loadup to MAX.PAYLOAD. BUT NOT THE TESTBENCH / APPS in simulation!
Yes. As in my previous reply, the testbench provides simple method to do basic testing and this does not cover all the traffic profile stimuli. If user wants to simulate with what is not covered in the testbench, user has to modify the testbench based on their requirements.
So, i think i am on the edge of improving the testbench and APPS to payload = max.payload. My question: if i would share this code with you, would INTEL be willing to compensate me for this effort ? (i think INTEL does not deliver what it says it does as described in the manual)
I apologize for the miscommunication if there is any. The reason I asked if you are willing to share the modification earlier is because there are some hobbyists share information, what they have created or method to solve problems in this public forum. Please do not share if the content is confidential or non-public accessible.
Thanks for your understanding. Do let me know if you have any questions or concerns.
Best regards,
KhaiY
Occasional ContributorDear KhaiChein_Y, thanks for reaching out.
I assume the name of the zipfiles speak for its content.
Main changes:
- splitted altpcietb_bv_rp_gen2_x8 into two files: altpcie_bfm_rpvar and altpcietb_bv_rp_gen2_x8_ex_rpvar, to make the editing of the last more easy
- added many $fdisplay statements to more easily track bitstreams (i always get lost in the wave screen)
- changed a lot in tlp_parser to generate headers for 8 byte CplD. The result of that can e.g. be seen in outparsout.txt
- added 8 byte wide write to and read from memory (interconnect_low and ~high, and mem_low and ~high) in pcie_ed
- changed a bit in downstream_driver to generate 8 bytes.
- in pcie_ed, line 546 and 566, 1 is added to each read byte
- In the downstream_drive file, line 465, Length = 4, as written by INTEL. If you run the testbench, it fails of course because of the adding of 1 to each byte. But downstream_drive is modifies such, that it does not stop, it just reports a difference.
- Change this line 465 to 8, and the tb sends 8 byte, the apps writes it to MEM in pcie_ed, read it back, adapts the TLP headerfiles, of which you can see the result in pcie_ed_tx.txt, and eventually sends seemingly correct data to the HardIP.
- At receipt in TB, in rpvar, rx_data remains zero, but rx_desc0 has some recognizable values. Also, there are 'x' in the serial wires tx0..3 from the DUT, to the rx0...3 of rpvar. This suggests that the HardIP of PCIE is not controlled correct by TLP headers? configuration setting?
- I hope this clarifies, please do not hesitate to ask clarification if needed.
Regards ,Pieter
Occasional ContributorDear KhaiChein_Y
I did not receive a reaction from you yet. Please respond.
Regards, pieter
- PVanL
Dear KhaiChein_Y
Can you give me an update where you stand, or how i can help you, if at all, with getting the simulation running? regards, Pieter (....i am trying not to sound impatient.....)
