New ContributorPCIe DMA Testbench Generation Issue
We need to integrate PCIe Gen2x1 and DDR3 via DMA. So we generated a PCIe Gen2x1 and we tried to add PCIE DMA Controller 64 and Avlon MM clock crossing bridge to access DDR3 memory of 2G space. But while generating testbench we are getting the error on differences in address mapping. While we are trying address 2GB of data, testbench is trying to address 4GB and we get a mismatch in address range. Could you please check these issues?.
I have attached the project file and screen error screen shot for your reference.
Hello Sir,
The reason is that you export the master port of the clock crossing bridge. And the BFM in default will generate the address 32bits. What you need to do is add the BFM slave manually and set the address to 30bits. And turn on the burst on burst boundaries only option. Then connect the CC bridge and the BFM slave clock and reset from the system. With this. The testbench can generate correctly. Attach the modified qsys file.
