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Sudhirkv's avatar
Sudhirkv
Icon for New Contributor rankNew Contributor
6 years ago
Solved

PCIe DMA Testbench Generation Issue

We need to integrate PCIe Gen2x1 and DDR3 via DMA. So we generated a PCIe Gen2x1 and we tried to add PCIE DMA Controller 64 and Avlon MM clock crossing bridge to access DDR3 memory of 2G space. But ...
  • BoonT_Intel's avatar
    BoonT_Intel
    6 years ago

    Hello Sir,

    The reason is that you export the master port of the clock crossing bridge. And the BFM in default will generate the address 32bits. What you need to do is add the BFM slave manually and set the address to 30bits. And turn on the burst on burst boundaries only option. Then connect the CC bridge and the BFM slave clock and reset from the system. With this. The testbench can generate correctly. Attach the modified qsys file.

BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Sir,

The reason is that you export the master port of the clock crossing bridge. And the BFM in default will generate the address 32bits. What you need to do is add the BFM slave manually and set the address to 30bits. And turn on the burst on burst boundaries only option. Then connect the CC bridge and the BFM slave clock and reset from the system. With this. The testbench can generate correctly. Attach the modified qsys file.

  • Sudhirkv's avatar
    Sudhirkv
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    Thank you for your response. We added the Avalon-MM slave BFM and set the parameters as advised by you and we were able to successfully create testbench system for the design.

    We could see a read transaction in the Avalon MM slave BFM but the Read response is always driven as X. Attached is the screenshot for the same. Could you please let us know how to proceed with this?

    I will also add the QSYS file of the design for your reference.