Hi dsl,
Thanks for your reply.
I am working on FPGA design and Ritesh is developing PCIe driver from Host Side.SDHC IP Core has both Avalon Slave and Avalon Master Interface.Avalon Slave interface is used to configure register of SDHC IP Core(including DMA registers) and Avalon Master Interface is used to transfer data between SDHC IP Core and other Avalon Slave Interface.Normally we connect SDHC IP Core Avalon Master Interface to Avalon Slave Interface of Memory Controller.However in this design,we don't have any external memory.(Onchip Memory is used for testing purpose only).In actual design there will be only two IP Core,one for PCIe and other for SD
Card.In existing design,I have connected SDHC Avalon Master Port to Txs port of the PCIe IP Core (took reference from PCIe User Guide example). Please see the attached Qsys design connection.Now we don't know how to access Txs port from the Host Side PCIe driver.
Would you please provide your suggestions.
Thanks,
Krupesh