Forum Discussion
New ContributorPCIe design reference recommendation (Cyclone 10 GX)
Hi Derek,
Can I understand it in this way: Before starting the DMA transfer, the computer driver needs to edit this translation table according to the DMA descriptor table first. In this way, during the DMA transfer, the bridge can convert the avalon-mm address passed in through the txs interface into the physical address of the memory applied by the computer driver for DMA.
>> Yes, your understanding is correct. Before initiating a DMA transfer, the computer driver typically needs to configure the address translation table within the PCI Express Avalon-MM bridge. This configuration ensures that the addresses used in the DMA descriptor table are correctly mapped to the physical addresses in the system memory.The board I designed is a Gen2x1 PCIe board. If I generate an IP core of "Avalon-MM with DMA, Gen2x4", can it be used for my board?
>> Theoritically, you can use a Gen2x4 IP core with a Gen2x1 board, the system will operate with only one lane active, limiting the bandwidth to that of a Gen2x1 configuration. Make sure to adjust any settings in the IP core or driver to reflect the actual lane count supported by your hardware.
Regards,
Wincent_Altera
Regular ContributorHi Derek,
If you using Cyclone 10 GX and you need AVMM - DMA design.
You may refer to Intel® Cyclone® 10 GX FPGA – PCIe* 2.0 x4 DMA Design Example
If your slot is gen2x2, by right the host will auto degrade from x4 to x2 is you slot into x2 slot.
For this design, only Linux version of driver is provided.
Detail about the design guide you may refer to https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/installing-the-dma-test-driver-and-running.html
Regards,
Wincent_Altera
New ContributorHi Wincent,
Thank you very much for your reply and help.
When I was reading the document "Arria10 and Cyclone10 GX Avalon Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide", I have a question to ask.
The document mentions an Avalon-MM-to-PCI Express Address Translation Table. It introduces the control registers of the PCI Express Avalon-MM bridge. Among the registers in the address range of 0x1000 - 0x1FFF, only the Avalon-MM-to-PCI Express address map entry is mentioned. May I ask where this translation table is actually stored?
In addition, does the computer driver need to edit this translation table?
Can I understand it in this way: Before starting the DMA transfer, the computer driver needs to edit this translation table according to the DMA descriptor table first. In this way, during the DMA transfer, the bridge can convert the avalon-mm address passed in through the txs interface into the physical address of the memory applied by the computer driver for DMA.
There is another question I'd like to ask. The board I designed is a Gen2x1 PCIe board. If I generate an IP core of "Avalon-MM with DMA, Gen2x4", can it be used for my board?
- Wincent_Altera
Hi Derek,
Can I understand it in this way: Before starting the DMA transfer, the computer driver needs to edit this translation table according to the DMA descriptor table first. In this way, during the DMA transfer, the bridge can convert the avalon-mm address passed in through the txs interface into the physical address of the memory applied by the computer driver for DMA.
>> Yes, your understanding is correct. Before initiating a DMA transfer, the computer driver typically needs to configure the address translation table within the PCI Express Avalon-MM bridge. This configuration ensures that the addresses used in the DMA descriptor table are correctly mapped to the physical addresses in the system memory.The board I designed is a Gen2x1 PCIe board. If I generate an IP core of "Avalon-MM with DMA, Gen2x4", can it be used for my board?
>> Theoritically, you can use a Gen2x4 IP core with a Gen2x1 board, the system will operate with only one lane active, limiting the bandwidth to that of a Gen2x1 configuration. Make sure to adjust any settings in the IP core or driver to reflect the actual lane count supported by your hardware.
Regards,
Wincent_Altera
