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Altera_Forum's avatar
Altera_Forum
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14 years ago

pcie can't perform memory write trasaction from endpoint to rootpoint

Hi, I generated tow pcie cores by pcie compiler, one as rootpoint and another as endpoint. I configured the rootpoint and endpoint well. I can perform the memory write transaction from rootpoin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I generate a memory read request from root port to the end port. The end port gets the read requeset and returns a completion to the root port. And in the rx_st interface of the root port, we get the completion. It likes that the bus id and device id are correct.

We can't send the memory write request from end port to the root port, maybe I didn't configure the bar of the root port and the Memory Base and Memory Limit registers correctly :mad:

Does anyone know how to configure the registers related to the address routing ?

Thanks,

Long