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JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

PCIe "Asynchronous Clock" design on A10 FPGA

Hi, Is there any example design for PCIe HIP that uses asynchronous clock as pcie reference clock in A10 fpga ? Generally PCIE HIP is required to use the 100 MHz reference clock from the Host PC...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY