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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

PCIe "Asynchronous Clock" design on A10 FPGA

Hi, Is there any example design for PCIe HIP that uses asynchronous clock as pcie reference clock in A10 fpga ? Generally PCIE HIP is required to use the 100 MHz reference clock from the Host PC...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Do you mean to connect the refclk pin to internal FPGA generated clock? The input reference clock, refclk, must be stable and free-running at device powerup for a successful device configuration.


Thanks

Best regards,

KhaiY