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RWitt's avatar
RWitt
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7 years ago

PCIe a10_hip Several issues: MSI-X conduit/signals not exposed in non-SRIOV mode, no Gen3@8Gbps training (can't get past 5Gbps), Configuration space "capabilities" enabled but not selected in PD, etc.

I have several posts/questions raised on the FPGA Tools community because I assumed I was having issues configuring the PCIe IP in Platform Designer. Just in case this is the better forum I'll raise ...
RWitt's avatar
RWitt
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7 years ago

My update 12/05/18

a) it does not make any sense that you would have to have at least one VF when using the SR-IOV core.

Solution/Answer: I spent the day changing parameters and have found how to link at 8Gbps. In the "Parameters" settings tab, under the "PHY Characteristics" tab I first enabled the "Soft DFE" thinking that would help and it didn't (but I left it selected). I then checked the "Enable RX polarity inversion soft logic" box and enabled that. That was the answer, I successfully linked at 8Gbps. I then built again turning that polarity inversion off and I could only link at 5Gbps. So, there is something about the SR-IOV wrapper that makes the link bring-up different.