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ASHWINI
New Contributor
New ContributorPCI Scrambler
we are developing some custom PCIe application where we can't use hard PCI ip so as which will be tested on stratix 10 SX dev kit. while searching scrambeler in intel exmple code for PCI we got one ...
Nathan_R_Intel
Contributor
ContributorHie,
My apologies for the delayed first response. I got your case mixed up with another PCIe forum question; hence I missed providing an update.
I am sorry, but I cannot identify which portion of our IP, reference design or Quartus version where you have obtained this .v file from. Anyway, for Intel-FPGA's PCIe IP,
the polynomial used is a degree 23 polynomial for LFSR for scrambling.
For this .v file, it has data_out width of 32 bit. pld_if_dw is parameter specifying the interface data-width. words_pld_if is another parameter to specify the scrambler data enable width.
Regards,
Nathan
