Hie,
My apologies for the delayed first response. I got your case mixed up with another PCIe forum question; hence I missed providing an update.
I am sorry, but I cannot identify which portion of our IP, reference design or Quartus version where you have obtained this .v file from. Anyway, for Intel-FPGA's PCIe IP,
the polynomial used is a degree 23 polynomial for LFSR for scrambling.
For this .v file, it has data_out width of 32 bit. pld_if_dw is parameter specifying the interface data-width. words_pld_if is another parameter to specify the scrambler data enable width.
Regards,
Nathan