Honored Contributor
Honored ContributorI think the confusion is regarding what happens to the "garbage" data inserted to adhere to the data alignment requirements of the core. Any "garbage" data inserted on the Avalon side to adhere to the data alignment guidelines will not be transmitted on the PCIe link. Since this garbage data is not transmitted on the link, the address specified in the header is referring to the first valid piece of data, not the "garbage" data. Likewise, the first dword byte enable in the header refer to the first valid dword of data, not any "garbage" data.
Using your specific example, although you are using a 3DW header, the 4th dword seen at the Avalon streaming interface would contain some "garbage" data. Even though the "garbage" data exists on the Avalon interface, this "garbage" data will not be transmitted on the PCIe link. As a result, the destination address of the first valid dword of data you send will be 1000h. Similarly, the 1st DW byte enable refers to the 1st dword of valid data after the "garbage" data. So, assuming all four bytes of the 1st dword of valid data are to be written, the 1st DW field will be set to 0xF in the header. Does this help clarify?
