Honored Contributor
Honored ContributorSorry for the confusion on the address point. I will try to clarify what the documentation is saying. Note that what I will describe below assumes the following:
* 64-bit AV-ST interface on the backend of the PCIe hard ip core * packet payload length of 4 dwords When your starting address is a 32-bit non-QWORD aligned address, your packet will look like: DW0: packet header dword0, SOP=1, EOP=0 DW1: packet header dword1, SOP=1, EOP=0 DW2: packet header dword2, SOP=0, EOP=0 DW3: payload dword0, SOP=0, EOP=0 DW4: payload dword1, SOP=0, EOP=0 DW5: payload dword2, SOP=0, EOP=0 DW6: payload dword3, SOP=0, EOP=1 DW7: don't care, SOP=0, EOP=1 When your starting address is a 32-bit QWORD aligned address, your packet will look like: DW0: packet header dword0, SOP=1, EOP=0 DW1: packet header dword1, SOP=1, EOP=0 DW2: packet header dword2, SOP=0, EOP=0 DW3, don't care, SOP=0, EOP=0 DW4: payload dword0, SOP=0, EOP=0 DW5: payload dword1, SOP=0, EOP=0 DW6: payload dword2, SOP=0, EOP=1 DW7: payload dword3, SOP=0, EOP=1 When your starting address is a 64-bit non-QWORD aligned address, your packet will look like: DW0: packet header dword0, SOP=1, EOP=0 DW1: packet header dword1, SOP=1, EOP=0 DW2: packet header dword2, SOP=0, EOP=0 DW3: packet header dword3, SOP=0, EOP=0 DW4: don't care, SOP=0, EOP=0 DW5: payload dword0, SOP=0, EOP=0 DW6: payload dword1, SOP=0, EOP=0 DW6: payload dword2, SOP=0, EOP=0 DW7: payload dword3, SOP=0, EOP=1 DW8: don't care, SOP=0, EOP=1 When your starting address is a 32-bit QWORD aligned address, your packet will look like: DW0: packet header dword0, SOP=1, EOP=0 DW1: packet header dword1, SOP=1, EOP=0 DW2: packet header dword2, SOP=0, EOP=0 DW3: packet header dword3, SOP=0, EOP=0 DW4: payload dword0, SOP=0, EOP=0 DW5: payload dword1, SOP=0, EOP=0 DW6: payload dword2, SOP=0, EOP=1 DW7: payload dword3, SOP=0, EOP=1 The example should illustrate that it is not the number of dwords in the header that defines how the data is aligned in the dwords of the avalon packet that you transmit to the PCIe core. Instead, it is the address that defines the alignment.
