Honored Contributor
Honored ContributorWe have 3 BARs (0, 2, 3 and 4) - largely to do with no one standing back from the design far enough! since BAR4 covers 16MB SDRAM and some IO and everything else would fit in the spare space.
The other BARs are much smaller. One of the BARs maps some stuff that has avalon addresses between 0x40000000-0x4003ffff this is (probably) a 256b BAR. There was a problem with BAR4, the signals are fed through a conduit because the auto-assigned BAR ended up having extra unwanted address lines and was larger than 32MB (I'm not sure of the exact details). Actually, you could probably use a conduit to feed in the high address lines between the PCIe Avalon masters and any avalon slaves. We do currently has an 'interesting' issue when we do PCIe reads of locations that don't have an Avalon slave. Not sure what the fpga does, but it sure confuses the little ppc at the other end!
