PCI express reference design doesn't complete

After debugging the reference design (Thanks Altera :rolleyes: ). I believe the issue is to do with the data word length counter in the rx_pcie.v file within the application section.

On line 449 it says

always @(Rx_St_Sop)

rx_modlen = rx_dwlen;

I changed this to

always @*

rx_modlen = rx_dwlen_reg;//rx_dwlen;

The rx_dwlen changes as the data goes through the RX_Data_A registers. Although the process should only be sensitive to the pulse of "Rx_St_Sop" it seems to follow the rx_dwlen changing value. This means that the burst size out to the DDR memory becomes 1. The read following it is one as well. the simulation fails because the data does not match with what it was expecting. i.e. 16 dwords.

Using the "rx_dwlen_reg" holds the correct value allowing the simulation to work as it should.

Chris