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Altera_Forum's avatar
Altera_Forum
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18 years ago

PCI Express: configuration

Hi all, I'm working on the transaction layer of my custom PCI Express IP. The problem is that when I answer to the Config Read T0 request from de root complex, with a Completion W/ Data contain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

Thanks for your answer.

For a Configuration Read, TC and Attr should be zero.

I use the Requester ID I received: 0x0000, so the Completer ID is 0x0100 and I put it in the completion. EP, BCM, CS and TD are 0. The length is 1, the Byte Count for IO and Configuration Completions is always 4. Lower address is 0. So I really don't understand the problem. Especially, I checked with the Catalyst SPX software: I compared my completions and there is no reason apparently. Anyway I'll put the TLP I receive and the one I send:

From the chipset:

Start-Sequence N

FB -0001

FMT/Type-Length-Requester ID-Tag/BE-Bus/Dev/Fct-Reg Number - CRC

0400 -0001 -0000 -0503 -0100 -0000 -780381B7

End

FD

I reply with:

Start-Sequence N

FB -0000

FMT/Type-Length-Completer ID-BCM/BCOunt-Requester ID- Tag Lower Address

4A00 -0001 -0100 -0004 -0000 -0500

- Data - Crc

-A2150300 - .....

End

FD

The Chipset ACK my Completion but no further actions are processed.