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Altera_Forum's avatar
Altera_Forum
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13 years ago

PCI Express Avalon ST transmit with breaks in data flow

Hi all, I ran into a problem here when using the Stratix IV GX Hard IP. I start sending a packet to the IP using the TX channel Avalon-ST. As specified in the Avalon-ST spec, a valid cycle is i...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I 100%ly agree. And I don’t understand why this feature is not supported by Antera – most other PCIe IP vendors do support this, or even allow to differentiate between a buffered transaction that allows this signal to be de-asserted arbitrarily, and an unbuffered transaction that behaves as required by Altera.