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Altera_Forum's avatar
Altera_Forum
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13 years ago

PCI Express Avalon ST transmit with breaks in data flow

Hi all, I ran into a problem here when using the Stratix IV GX Hard IP. I start sending a packet to the IP using the TX channel Avalon-ST. As specified in the Avalon-ST spec, a valid cycle is i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the response. I was suspecting something like this. It would be nice if the documentation stated it more clearly in the tx_st_valid signal description.