PCI-E gen3 HIP simulation

I am also facing the same problem with Quartus 12.0 sp1.

For the ip generated through megawizard for verilog, I ran vsim in the <ep>_sim/mentor directory

source msim_setup.tcl in vsim

ld_debug

and I see simulation exiting with errors like

instantiation of stratixiv_hssi_gen3_tx_pcs_encrypted failed. The design unit was not found.

where can find this module?

Alternately, I generated vhdl version of the PCIe core gen 3 and executing the same command ld_debug yielded this error.

Fatal error in a protected context.

Time 0 ps Iteration Protected: /ep_g3_x8_avl_256_a_s5_inst/<protected> File: nofile

FATAL ERROR while loading design

Any ideas/solutions about VHDL simulation failure would be highly appreciated.

Thanks,

Fasahat