Parallel Flash Loader (PFL) IP Core Timing Constrains

Hallo sstrell

Thanks for your reply. For Example if set the flash_nce path as false path, as suggested in the pfl user guide, on the time constrains report it shows that flash_nce path is partially constrained. I am attaching the screen shots of the timing analyzer report that i get when i set the flash_nce as a false path. Setting the other paths mentioned in first post also produces same kind of behavior. I am also attaching the report from the timing analyzer. You can open the file with notepad.

Let me know if this information is enough for you, to find the problem or you need some more information.