Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorParallel Flash Loader (PFL) IP Core Signals
Hallo I am making a PFL IP core for a MAX V CPLD. When i look at the user guide on the following link https://www.altera.com/documentation/sss1411439280066.html#sss1458191622012 there...
Altera_ForumHonored Contributor
Honored ContributorDear sstrell
thanks again for your quick and perfect answer. Another signal that is making me confused is the fpga_init_done signal from the following pdf https://www.altera.com/en_us/pdfs/literature/wp/wp_max_flash.pdf But i could not find this signal in PFL IP core user guide. So i am bit confused about this signal also.
