Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Parallel Flash Loader For MAX II .

Hi Everyone, I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash. I have been able to generate the IP by following AN478 and AN386. I have i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

--- Quote Start ---

Hi,

My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

Not required.

--- Quote End ---

what are you trying to do with test bench?

if you wish to configure FPGA then refer previous post.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)